With consumer electronics and IoT devices constantly pushing for greater capability in smaller sizes, stacking boards can solve these demands through vertical rather than lateral expansion. This allows fitting elaborately multilayered and dense designs into shrinkingly thin packages.
However, transitioning from single PCB products to interconnecting stacked boards in 3D assemblies introduces new complexity in layout, error-proofing, manufacturability, and reliability assurance.
By following these 12 fundamental design rules for stacked configurations discussed below, engineers can avoid common mistakes and harness maximum benefit from multilayer PCB stacking techniques.
Rule 1: Define Interconnection Architecture
The first step in planning any stacked board system should focus on mapping the required electrical connectivity between layers based on circuit blocks and signals needing to transition across stack boundaries.
Several approaches exist for routing links between boards:
- Require mating connectors on each layer
- Provide reconfigurability
- Add cost and thickness
**Flex Circuit Interposers **
- Thin, bendable flex layers route signals
- Maintain flexibility between rigid boards
- Allows complex branching
Board Stacking Headers
- Female sockets solder onto boards
- Males pins interconnect vertically
- Limit connections available
Castellated Plated Half-Holes
- Extended pads on board edges
- Solder joints bridge layers
- Compact and simple
Select architecture based on connection density needs, whether stacking aims for modularity versus minimized thickness, shock/vibration environment, and end application.
Rule 2: Partition Logical Blocks to Boards
Allocation of circuit functions across discrete PCB layers in the stack requires strategic optimization based on:
- Related components placed locally
- Noise sensitive circuits isolated
- Shared power regulated separately
- Critical links routed point-to-point
Well-planned partitioning minimizes inter-board connections needing tier-spanning resources. This reduces parasitic loading on signals crossing boundaries.
For complex systems, model different partitioning schemes for performance tradeoffs before layout.
Rule 3: Define Board Roles and Connectivity
With circuits divided by logic blocks, define essential connectivity pathways between layers based on functional chains needing:
- Processors → Memory flows
- Bus links between controllers
- Switching supplies → Local regulators
- Noise-sensitive domains isolated
- Reference clocks → RF synthesizers
- Analog sensor signals → ADCs
Map boards into senders, receivers, and any required “repeater” layers, like buffered signal re-drivers or voltage regulators that facilitate inter-plane connectivity.
Rule 4: Stack Thin Dielectrics for EM Control
Managing electromagnetic radiation becomes more critical when embedding increased functionality spanning across metal-filled board layers.
Stacking multiple high-frequency digital planes demand adequate shielding and filtering between radiating circuits through:
- Multiple ground planes
- Thin dielectric layers
- Tight layer-to-layer registration
Keep glass dielectrics under 3 mils thickness between adjacent power and signal layers wherever possible. This prevents emissions coupling into sensitive analog or radio receivers in dense designs.
Rule 5: Define Layer Registration Accuracy Needs
Extending high pin count interfaces between rigid boards requires precision alignment to mate connectors across stacking boundaries.
The smaller pad/pin pitches involved, the tighter allowable mechanical registration tolerances become.
Small misalignments between layers accumulates into large position skew
Sub-100 micron registration loses connectivity – establish alignment needs early when evaluating contractors.
Rule 6: Manage Differential Expansion and Contraction
While PCB substrates themselves possess minimal thermal expansion, even small coefficients of thermal expansion (CTE) mismatches between boards and components multiply into substantial mechanical stresses over temperature.
This requires deliberately managing CTE differences in stacked designs through:
- Defined keepout zones around interfaces
- Floating connector pin joints
- Flexible adhesive choices between layers
- Characterized thermal cycling protocols
Rule 7: Define Layer Order and Chicken Footprints
Establish a consistent stacking order between boards ensuring:
- Mating connectors align properly
- Keepouts reserved for components
- Airflow passages reserved
- Labels remain visible
Chicken footprints paint exact board geometries, holes, and placements for reference:
Full assembly model visualizing multi-board 3D envelope
This helps anticipate and resolve collisions early across complex, opaque stacks.
Rule 8: Model End Assembly Envelope
Fully visualizing the 3D volumetric envelope helps make space allowances for:
Stacked Board Dimensions
- Vertical height
- Consult layer thickness tolerances
- Tall passives/connectors
- Fan/cable spaces
- Standoff screws
- Gaskets, labels
- Wall clearances
Use accurate 3D models of boards, parts, enclosure to preview all stackup fittment, alignment, and assembly sequences.
Rule 9: Define Interlayer Interconnect Density
While stacked configurations aim for increased functionality in constrained volumes, engineers must pragmatically assess technical capabilities and costs when determining interconnection densities between layers.
High density board-to-board connectors spanning 1000+ pins demand complex, high layer count routing both between and within planes. This escalates fabrication and lamination processes required.
Strike the right balance between optimizing vertical interconnect density without manufacturing yield losses from brittle PCBs prone to layer misregistration and buried shorts.
Rule 10: Control Impedances Across Layers
Maintaining matched impedances across signaling links between rigid boards proves vital for error-free interconnection.
Avoid sudden intra-system impedance discontinuities by:
- Extending layer stackups through flex layers
- Balancing stackup asymmetry
- Defining connector pinouts early
- Simulating heavily loaded channels
Watch for ground noise voltages adding in series across boards corrupting low-level signals.
Rule 11: Streamline Test and Debug Access
While stacking inherently buries debug/programming headers between layers, ensure stack designs facilitate necessary:
- Place programmers along accessible edges
- Route to external connectors
Design For Test Circuits
- Include layer test points
- Control impedances to scopes
- Ensure firmware upgradeability
- Access processor communication buses
This averts needing to fully disassemble complex stacks when troubleshooting issues.
Rule 12: Review Manufacturing Capabilities
The intricacies involved in registering and laminating multilayer board stacks demands advanced PCB fabrication expertise, with key considerations:
- 4+ mil alignment typical
- Tighter tolerances cost more
- Staggered vias prone to failure
- Optimize drilling angles
- Thin dies risk cracked traces
- Define minimum bend rules
Vet candidate factories on successfully demonstrating stacked board samples before committing whole orders.
Properly harnessing stacked PCB techniques provides demonstrable space and functionality advantages across product categories from phones to aerospace avionics.
By judiciously following fundamental design for manufacturing guidelines suited for interlayer connectivity constraints, engineers can effectively architect multilayer board systems ready for volume production.
Consult the rules covered here when planning your next ambitious multilayer PCB project!
Stacked Board Design FAQs
Here are some common questions around designing stacked board assemblies:
Q: How many PCBs can be vertically stacked?
A: The practical limit falls around 5-6 rigid layers before thickness, alignment complexity, and thermal dissipation burdens start diminishing returns on adding more boards.
Q: What are recommended layer thicknesses for stacking?
A: Good thicknesses for simpler 4-6 layer consumer boards range from 0.4mm on the low end up to 2.4mm maximum. High layer count telecom or server boards approach 1mm typically.
Q: How do designers prevent EMI issues in dense stacks?
A: Careful stack planning to isolate radiating circuits across boards helps. Many stacks also sandwich mid-layers as ground planes for shielding with multiple vias stitching planes together.
Q: What are the tradeoffs of flex circuit interconnects versus rigid pins?
A: Flex layers allow higher connection density and Manufacturability with complex layouts. But vertical pins enable hot swapping modular boards and thicker layers if needed. Select based on flexibility requirements.
Q: How are very dense board connectors aligned properly?
A: Precision machined alignment guide pins temporarily mate the stack together during soldering then disassemble leaving the self-registered connector joints in place.