High speed PCBs operating above 1GHz frequencies require careful layout practices to ensure signal integrity and avoid issues like crosstalk or radiated emissions. This guide provides an overview of key high speed design techniques including transmission line selection, layer stackup, decoupling, and EMI control that engineers should follow to develop reliable, high performance boards.

Characterizing High Speed Signals

Before optimizing the PCB layout, engineers must first characterize the signals. Key parameters include:

• Data Rates – How fast do signals switch? Faster edge rates need greater care.
• Rise Times/Fall Times – Duration of voltage transitions from 10-90%. Sub-nanosecond rise times indicate high speed design.
• Spectral Content – What is the frequency composition of square wave and complex waveform signals?
• Single-ended vs Differential – Differential signals help reject common mode noise.
• Swing Voltages – Lower signal voltages are more susceptible to noise coupling.
• Propagation Distance – Longer trace lengths increase radiation and pickup.
• Timing Budgets – How much jitter, skew, and delay can be tolerated?

Simulations, calculations, and measurements of driving devices establish these critical parameters that guide PCB layout.

Selecting Dielectrics, Laminates and Copper

Several key material choices support high speed signal propagation:

Laminate Dielectric Constant

Lower dielectric constants near 3 to 4 provide tighter impedance control and lower loss, especially above ~5GHz. Common RF materials include:

• Rogers 4003C or 4350B
• Taconic RF-35 or XLam
• Isola Astra MT77
• Panasonic Megtron 6

Low Loss Materials

Greater lamination thickness increases loss. Low loss tangent (<0.005) laminates keep attenuation in check.

Tight Dielectric Tolerances

Consistent dielectrics (tight Dk and DF tolerances) are necessary to achieve matched impedances between PCBs and across fabrication lots.

Thermal Management

High power signals require laminates with thermal conductivity ≥0.5 W/m/K to spread heat.

Layer Stackup

Proper sequence, thickness, and orientations of dielectric materials and copper layers prevents asymmetric propagation.

Smooth Copper and Prepregs

Rough copper foil and resin coating variations impact propagation, loss, and impedance consistency.

Modeling Transmission Lines

Accurate transmission line models set the foundation for proper impedance control and performance.

Selecting Line Type

Microstrip, stripline, and differential pair geometries each have advantages and disadvantages at higher frequencies.

Accounting for Losses

Models must factor in conductor, dielectric, and radiation losses to determine insertion loss performance.

Simulating High Frequencies

Full wave 3D EM simulators are required for modeling complex geometries at multi-GHz frequencies.

Modeling Non-Idealities

Effects like surface roughness, anisotropy, and tolerance variations must be included in simulations.

Key Route Length Matching

Matching electrical lengths tunes propagation delay between signals to eliminate timing skews. Some common techniques include:

• Matching route lengths on parallel bus lines
• Lengthening faster routes by adding serpentine segments
• Adding meanders at low impedance areas like 0V planes
• Using grids to align length and spacing

Impedance Matching and Termination

Mismatched loads and improperly terminated traces cause harmful reflections. Proper termination improves signal quality:

• Series termination near source
• Parallel termination at load
• Matched line and load impedance
• Resistive vs. capacitive loads
• Thevenin termination networks

Bypassing and Decoupling

Each powered IC needs dedicated bypass capacitors placed close to leads for stable voltage regulation. Follow these guidelines:

• 0.1uF ceramic caps minimize high frequency noise
• 10uF+ electrolytics handle low frequency fluctuations
• Ground-side placement reduces ground lead inductance
• Multiple vias ensure low inductance pads
• Distribute caps across voltage planes

Stackup Construction

A well engineered layer stackup is crucial for signal integrity:

• Adjacent ground/power planes for controlled impedance environments
• Solid reference planes without cuts if possible
• Component placement on outer layers
• Differential pairs isolated by ground planes
• Thicker dielectrics for lower loss
• Thinner dielectrics when maximizing layers

Grounding and Power Distribution

Proper grounding and power delivery design prevents unstable circuit operation:

• Impedance controlled distribution network
• Flooded copper planes for low inductance
• Proper board/chassis grounding
• Segmented power planes to isolate noise
• Components placed near associated power pins
• Multi-point ground connections

Isolation Techniques

Crosstalk coupling must be reduced between sensitive traces:

• Increased spacing to adjacent traces
• Ground or power plane shields between signals
• Lower dielectric constant material around traces
• Avoid running aggressors and victims in parallel
• Crosstalk barriers to decouple traces
• Skew lines to control edge coupling

EMI Mitigation

High speed signals can cause unwanted emissions or couple external interference. Some EMI techniques include:

• Series termination to prevent reflections
• Embedded capacitance to suppress resonances
• Very low loss laminates to curb dielectric absorption
• Smaller vias and pads to reduce coupling apertures
• Partial power plane cuts only where needed
• Board level shielding and compartmentalization
• Chassis integration for full system shielding

SI Simulation and Verification

Running signal integrity simulations and measuring results is key:

• Calculate propagation loss, dispersion, and skew
• Model discontinuities like vias, connectors, bends
• Perform time and frequency domain analysis
• Verify termination and impedance matching
• Run worst case simulations across tolerances
• Measure S-parameters, eye diagrams, and jitter

Good correlation between simulated and measured results validates proper high speed design.

Design Rule Checking

Design rule checks tailored for high speed boards enforce constraints:

• Component placement on grid for length matching
• Minimum plane rule distances
• Limits on unsupported trace spans
• Minimum feature sizes for impedance needs
• Plane splits aligned with part placements
• Filtered part lists by speed grade

Manufacturing and Material Control

Tight tolerances and attention to materials are mandatory:

• Pre-production qualification of laminates
• Consistent dielectric materials from lot to lot
• Review glass weave skew and resin distribution
• Ensure copper surface roughness control
• Document fabrication process steps
• First article inspection and metrology

FQA about High Speed PCB Design

What makes a PCB high speed?

Frequencies over 1-2 GHz with fast rise times under 1 ns often define high speed designs needing additional SI analysis.

What dielectric constant is optimal for high speed?

Lower Dk around 3-4 provides better impedance control and lower loss than standard FR-4 dielectrics.

What causes reflection problems on traces?

Impedance mismatches between lines, loads, and terminations lead to signal reflections that distort waveforms.

How are high speed multilayer boards stacked up?

Core stackups alternate reference planes above and below routing layers to create shielded stripline environments.

Why is impedance matching important?

Careful impedance control maintains signal quality as frequencies rise and eliminates discontinuity reflections.

Conclusion

Designing reliable high speed PCBs requires managing loss, reflections, EMI, and other signal integrity effects through careful analysis, modeling, and material selection. When following disciplined layout techniques tailored to the data rates involved, high frequency boards can be engineered to perform well beyond GHz speeds. Partnering closely with an experienced PCB manufacturer is highly recommended to leverage lessons learned from previous precision RF and microwave designs.