Introduction

High density interconnect (HDI) PCBs utilize microvias to create interconnections between the thin laminated layers. These microvias come in three types – through hole vias, blind vias and buried vias. Using the right via structures is key to gaining the density benefits of HDI technology.

Blind vias connect inner layers to the surface layers above them. Buried vias only join internal layers without connecting to the outer surfaces. The constraints and layout guidelines for these two via structures differ from conventional through hole vias.

This article provides a reference on how to effectively leverage blind and buried vias in HDI designs to maximize routing capability. Key considerations for via placement, routing connections, layer planning, manufacturability, assembly and reliability are covered.

Blind Vias

Blind vias connect one or more internal conductive layers to only the adjacent outer layer:

• Provide access to internal layers without fully penetrating board.
• Allow high-density escape routing from inner layer components.
• Reduces via length compared to through hole via.

Locating Blind Vias

• Place blind vias directly over driven pins or pads.
• Arrange signal escape vias symmetrically around ground/power pads.
• Keep return current vias adjacent to signal vias if possible.
• Plan for test points to check inner layer connectivity.

Routing Blind Vias

• Connect to traces on top layer entering pad from side.
• Avoid traces overlapping blind via pad on top layer.
• Bottom layer trace can pass below via location.
• Add thermal reliefs to connect SMT pads.

Blind Via Layers

• Maximize use of closest inner layers first before adding more.
• Limit the number of connected layers based on aspect ratio.
• Thin cores allow a greater number of accessed layers.

Density Impact

• Allow routing out of densely packed ICs and BGAs.
• Enable more efficient breakouts from inner layers.
• Reduce overall via quantity vs through holes.

Buried Vias

Buried vias connect two or more internal layers without connecting to the outer surfaces:

• Provide interconnection between inner layers only.
• Eliminate stub length of routing up/down to outer layers.
• Allows positioning signals optimally within stackup.

Locating Buried Vias

• Place over contact pads or planes directly if possible.
• Avoid offsets greater than 50% of diameter.
• Allow for capture pads size on inner layers.

Routing Buried Vias

• No connection to top or bottom layers.
• Connect to inner layer pads/traces entering from the side.
• Route orthogonal traces between layers if needed.

Buried Via Layers

• Join non-adjacent inner layers that need interconnecting.
• Link components on inner layers directly through pads.
• Combine with blind vias to access additional layers.

Density Impact

• Reduces need for routing through outer layers.
• Optimizes high-speed signal layer placement.
• Lower stub effects compared to through hole vias.

Via Design Rules and Guidelines

Here are some key criteria to consider for blind and buried vias:

Placement

• Position over contact pads directly if possible
• Symmetrically place multiple vias
• Distribute evenly across component footprint

Routing

• Avoid traces overlapping pad on layers above
• Enter pads from the side on layers below
• Include thermal reliefs for SMT pads

Layers

• Connect closest required layers first
• Limit accessed layers based on aspect ratio
• More layers possible with thinner cores

Sizes

• Match drill bit capability, around 0.2mm min
• Balance pad size for layer requirements
• Similar pad sizes if stacking multiple vias

Separation

• 0.175mm min between adjacent vias
• 0.25mm min distance to pad edge
• 0.1mm min from any feature edge

Capture Pads

• Add 0.1mm annular ring capture pads
• May need enlarged pads on lower layers
• Allow for registration tolerances

HDI Layer Planning

Optimizing the layer stackup is key to maximize microvia benefits:

• Plan internal layer order based on connection needs
• Group signals with shared returns to contain routing
• Position very high speed channels innermost
• Assign power and ground planes next to high speed signals
• Alternate signal and plane layers to isolate signals
• Add thin core layers to increase via accessibility

Simulation can validate impedance, crosstalk and other attributes before final stackup commitment.

Manufacturing Guidelines

HDI fabrication constraints impact blind and buried via implementation:

• Laser drilling requires unobstructed access
• Limit blocked zones for drilling access
• Stagger overlapping BGA/QFN rows if possible
• Allow slightly oversized capture pads
• Minimize asymmetric pad shapes
• Watch for acid traps during copper etching
• Plating process should completely fill small vias

Reviewing the PCB manufacturer’s capabilities and design rules is advised.

HDI PCB Assembly

Assembling components on HDI boards with microvias requires attention:

• Tightly spaced vias can lead to solder wicking
• Flux outgassing can be a concern
• Solder paste volume needs to match via depth
• Inspect for even filleting within vias
• Consider glue dots under BGA/CSP parts
• Special warp controlling carriers may be needed
• Functional testers or ICT fixtures must reach buried layers

HDI assembly challenges necessitate close process control.

Reliability Considerations

Microvia reliability aspects:

• Thermal shock resistance
• Pad cratering prevention
• Protection against fracture with dynamic flexing
• Mitigating brittle intermetallic growth
• Resistance to electrochemical migration
• Vibration and drop shock resilience

Both design and manufacturing controls play a role in maximizing buried and blind via robustness and product life.

Blind and Buried Via Trade-Offs

Incorporating microvias requires balancing trade-offs:

Benefits

• High density routing from inner layers
• Fewer vias vs through holes
• Contain signals optimally
• Shorter stub connections

Challenges

• Limited component placement
• Complex breakout routing
• Narrow process margins
• Testing difficulties
• Repair constraints
• Higher fabrication cost

The advantages outweigh the additional effort in most HDI applications given the miniaturization and performance enabled.

Conclusion

Blind vias and buried vias are central in gaining many of the interconnect density benefits of HDI PCB technology. Using these microvia structures efficiently allows accessing inner layers, containment of high speed signals, layer count reduction and minimization of via stub lengths.

However, planning for manufacturability, assembly and reliability requires adapting layouts by following the constraints for via placement, capture pads, layer planning and stackup arrangement. When implemented appropriately, blind and buried vias provide a powerful tool for maximizing routing capability in space-constrained advanced PCBs.

Blind/Buried Via Design FAQs

Q: What is the minimum annular ring width recommended for buried vias?

A: For buried vias below 0.15mm diameter, use annular ring width of at least 0.1mm for sufficient landing area. Wider annular ring margins are advised when possible.

Q: How many layers can blind/buried microvias typically interconnect?

A: Aspect ratio constraints generally limit accessible layers to 1-4 depending on individual manufacturer’s process capability and registration accuracy. Thinner cores allow connecting more layers.

Q: Do buried and blind vias reduce PCB fabrication yield?

A: Yes, the tight tolerances can reduce yields versus standard through hole vias. But the yield loss is generally manageable with consistent processes. Testing also helps screen any defective vias.

Q: What considerations are important for HDI PCB repair and rework?

A: Repairing blind/buried vias and inner layers is extremely difficult. Ensure access for debugging vias and implement partitioned layouts limiting repair areas.

Q: How does reliability of buried vias compare to blind vias?

A: Buried vias only interfacing internal layers generally have better shock and vibration reliability. But factors like plating quality, capture pads, and routing connections also impact robustness.